The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for optical proximity correction for transistors using harmonic mean of gate length.
Optical lithography is a crucial step in semiconductor manufacturing. The basic principle of optical lithography is quite similar to that of chemistry-based photography. The images of the patterned photo-mask are projected through the high-precision optical system onto the wafer surface, which is coated with a layer of light-sensitive chemical compound, e.g. photo-resist. The patterns are then formed on the wafer surface after complex chemical reactions and follow-on manufacturing steps, such as development, post-exposure bake, and wet or dry etching.
The resolution of the photo-lithography system (R) can be described by the well-known Rayleigh's equation:
  R  =                    k        1            ⁢      λ              N      ⁢                          ⁢      A      in which λ is the wavelength of the light source, NA is the numerical aperture, and k1 is the factor describing the complexity of resolution enhancement techniques. As the very-large-scale integration (VLSI) technology pushes further into nanometer region, the feasible wavelength of the photo-lithographic system remains unchanged at 193 nm. Although there is anticipation that extreme ultraviolet lithography (EUVL) with the wavelength of 13 nm will replace traditional optical lithography, the availability of EUVL remains uncertain due to technical challenges and cost issues. On the other hand, the physical limit of dry lithography of NA is 1.0. The recently introduced immersion lithography has bigger NA (1.2), but it is harder to further increase NA to even higher values. Thus it is commonly recognized that k1 remains a cost effective knob to achieve finer resolution.
Due to the unavoidable diffraction, the optical lithography system is lossy in the sense that only low frequency components of the electromagnetic field can pass the optical system. Given a target layout of shapes that are desired to be manufactured, masks are generated that account for the non-linearities introduced by the lithographic process that prints wafer features that resemble the target. As the gap between the required feature size and lithography wavelength gets bigger, the final wafer images are quite different from the patterns on the mask. In the past few years, resolution enhancement techniques (RETs) have become necessary in order to achieve the required pattern density. One well-known RET is the optical proximity correction (OPC), in which the mask patterns are intentionally “distorted” so that the desired image can be formed on the wafer. Other commonly used RETs are sub-wavelength resolution assist features (SRAF) and phase-shift masks (PSM). Nowadays, considerable amount of computing power has to be dedicated to these post-layout processes (often referred as data prep).
The traditional method of performing OPC is called model-based OPC. Model-based OPC involves using models of optical and resist systems to simulate the wafer image of the mask. The simulation is followed by extracting the geometric error between the wafer feature and the target. The geometric error is called edge placement error (EPE). A cost function is defined as the summation of the EPEs across a layout and modifications of the mask are performed so as to minimize this cost function. A final mask solution is arrived at after several iterations of mask modifications and image simulations. The primary drawback of this type of mask modification is that it optimizes purely for geometric error between wafer and target features, which can often lead to non-optimal electrical performance. This problem is exacerbated by technology scaling, where the use of diffraction-limited optics coupled with variations in process conditions leads to higher electrical errors. Such errors are manifested in delay errors of individual logic cells and, at a more global level, errors in timing, which leads to a reduction in parametric yield.